第 4 章存储器映射.......................................................................................................................35

4.1 关于存储器映射 ..............................................................................................................35

4.2 Bit-banding........................................................................................................................37

4.2.1 直接访问别名区 ...................................................................................................38

4.2.2 直接访问 bit-band 区............................................................................................38

4.3 ROM 存储器表.................................................................................................................39

第 5 章异常...................................................................................................................................40

5.1 关于异常模型 ..................................................................................................................40

5.2 异常类型..........................................................................................................................41

5.3 异常优先级 ......................................................................................................................42

5.3.1 优先级 ...................................................................................................................43

5.3.2 优先级分组 ...........................................................................................................43

5.4 特权和堆栈 ......................................................................................................................44

5.4.1 堆栈 .......................................................................................................................44

5.4.2 特权 .......................................................................................................................44

5.5 占先..................................................................................................................................45

5.5.1 堆栈 .......................................................................................................................45

5.6 末尾连锁（Tail-chaining）.............................................................................................47

5.7 迟来..................................................................................................................................48

5.8 退出..................................................................................................................................49

5.8.1 异常退出 ...............................................................................................................49

5.8.2 处理器从 ISR 中返回...........................................................................................50

5.9 复位..................................................................................................................................51

5.9.1 向量表和复位 .......................................................................................................51

5.9.2 预期的启动顺序（boot up sequence） ...............................................................52

5.10 异常的控制权转移 ........................................................................................................54

5.11 设置多个堆栈 ................................................................................................................54

5.12 中止(abort)模型 .............................................................................................................56

5.12.1 硬故障 .................................................................................................................56

5.12.2 局部故障和升级 .................................................................................................56

5.12.3 故障状态寄存器和故障地址寄存器 .................................................................58

5.13 激活等级(activation level).............................................................................................59

5.14 流程图............................................................................................................................60

5.14.1 中断处理 .............................................................................................................60

5.14.2 占先 .....................................................................................................................61

5.14.3 返回 .....................................................................................................................62

第 6 章时钟和复位.......................................................................................................................64

6.1 Cortex-M3 时钟 ................................................................................................................64

6.2 Cortex-M3 复位 ................................................................................................................65

6.3 Cortex-M3 复位方式 ........................................................................................................65

6.3.1 上电复位 ...............................................................................................................65

6.3.2 系统复位 ...............................................................................................................66

6.3.3 JTAG-DP 复位 .......................................................................................................67

6.3.4 SW-DP 复位...........................................................................................................67